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data sheet 1 1999-10-07 built using the infineon multi-technology process spt ? which allows bipolar and cmos control circuitry plus dmos power devices to exist on the same monolithic structure. operation modes forward (cw), reverse (ccw), brake and high impedance are invoked from just two control pins with ttl/cmos compatible levels. the combination of an extremely low r ds on and the use of a power ic package with low thermal resistance and high thermal capacity helps to minimize system power dissipation. a blocking capacitor at the supply voltage is the only external circuitry due to the integrated freewheeling diodes. 1overview 1.1 features ? delivers up to 5 a continuous 6 a peak current ? optimized for dc motor management applications ? operates at supply voltages up to 40 v ?very low r ds on ; typ. 200 m w @25 c per switch ? output full short circuit protected ? overtemperature protection with hysteresis and diagnosis ? short circuit and open load diagnosis with open drain error flag ? undervoltage lockout ? cmos/ttl compatible inputs with hysteresis ? no crossover current ? internal freewheeling diodes ? wide temperature range; - 40 c < t j < 150 c description the tle 5205-2 is an integrated power h-bridge with dmos output stages for driving dc-motors. the part is type ordering code package tle 5205-2 q67000-a9283 p-to220-7-11 tle 5205-2gp q67006-a9237 p-dso-20-10 tle 5205-2g q67006-a9325 p-to263-7-1 tle 5205-2s q67000-a9324 p-to220-7-12 5-a h-bridge for dc-motor applications tle 5205-2 p-to220-7-11 p-dso-20-10 p-to263-7-1 p-to220-7-12
tle 5205-2 overview data sheet 2 1999-10-07 1.2 pin configuration (top view) figure 1 aep02513 out1 ef in1 gnd in2 s v out2 1234567 out2 out1 7 6 5 1234 in2 gnd in1 ef s v aep01991 tle 5205-2g tle 5205-2s aep01680 in1 in2 12 11 s v 1 2 3 4 20 5 19 6 18 7 17 8 16 9 15 10 14 13 gnd n.c. v s n.c. gnd ef q1 q2 gnd gnd n.c. n.c. n.c. n.c. n.c. n.c. n.c. aep01990 out1 ef in1 gnd in2 out2 s v 1234567 tle 5205-2 tle 5205-2gp
tle 5205-2 overview data sheet 3 1999-10-07 1.3 pin definitions and functions pin no. p-to220 pin no. p-dso symbol function 17out1 output of channel 1; short-circuit protected; integrated freewheeling diodes for inductive loads. 28ef error flag; ttl/cmos compatible output for error detection; (open drain) 39in1 control input 1; ttl/cmos compatible 4 1, 10, 11, 20 gnd ground; internally connected to tab 512in2 control input 2; ttl/cmos compatible 66, 15 v s supply voltage; block to gnd 714out2 output of channel 2; short-circuit protected; integrated freewheeling diodes for inductive loads. C 2, 3, 4, 5, 16, 17, 18, 19 n.c. not connected
tle 5205-2 overview data sheet 4 1999-10-07 1.4 functional block diagram figure 2 block diagram 1 0 0 1 1 1 0 1 0 2 z 1 0 0 1 z 0 1 0 2 in out error flag 1 7 ef in1 in2 2 3 5 4 6 out1 out2 gnd v s aeb02394 diagnosis and protection circuit 1 diagnosis and protection circuit 2
tle 5205-2 overview data sheet 5 1999-10-07 1.5 circuit description input circuit the control inputs consist of ttl/cmos-compatible schmitt-triggers with hysteresis. buffer amplifiers are driven by this stages. output stages the output stages consist of a dmos h-bridge. integrated circuits protect the outputs against short-circuit to ground and to the supply voltage. positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. a monitoring circuit for each output transistor detects whether the particular transitor is active and in this case prevents the corresponding source transistor (sink transistor) from conducting in sink operation (source operation). therefore no crossover currents can occur. 1.6 input logic truth table functional truth table in1 in2 out1 out2 comments l l h l motor turns clockwise l h l h motor turns counterclockwise h l l l brake; both low side transistors turned-on h h z z open circuit detection notes for output stage symbol value l low side transistor is turned-on high side transistor is turned-off h high side transistor is turned-on low side transistor is turned-off z high side transistor is turned-off low side transistor is turned-off
tle 5205-2 overview data sheet 6 1999-10-07 1.7 monitoring functions undervoltage lockout (uvlo): when v s reaches the switch on voltage v son the ic becomes active with a hysteresis. all output transistors are switched off if the supply voltage v s drops below the switch off value v soff. 1.8 protective function various errors like short-circuit to + v s , ground or across the load are detected. all faults result in turn-off of the output stages after a delay of 50 m s and setting of the error flag ef to ground. changing the inputs resets the error flag. a. output shorted to ground detection if a high side transistor is switched on and its output is shorted to ground, the output current is internally limited. after a delay of 50 m s all outputs will be switched-off and the error flag is set. b. output shorted to + v s detection if a low side transistor is switched on and its output is shorted to the supply voltage, the output current is internally limited. after a delay of 50 m s all outputs will be switched-off and the error flag is set. c. overload detection an internal circuit detects if the current through the low side transistor exceeds the trippoint i sdl . in this case all outputs are turned off after 50 m s and the error flag is set. d. overtemperature protection at a junction temperature higher than 150 c the thermal shutdown turns-off, all four output stages commonly and the error flag is set with a delay. e. open load detection the output q1 has a 10 k w pull-up resistor and the output q2 has a 10 k w pull-down resistor. if e1 and e2 are high, all output power stages are turned-off. in case of no load between q1 and q2 the output voltage q1 is v s and q2 is ground. this state will be detected by two comparators and an error flag will be set after a delay time of 50 m s. changing the inputs resets the error flip flop.
tle 5205-2 overview data sheet 7 1999-10-07 figure 3 simplified schematic for open load detection = = & 50 s m rs ff ef aes02395 v el eh v pull up 10 k w 10 k down w pull
tle 5205-2 diagnosis data sheet 8 1999-10-07 2 diagnosis various errors as listed in the table diagnosis are detected. short circuits and overload result in turning off the output stages after a delay t dsd and setting the error flag simultaneously [ef = l]. changing the inputs to a state where the fault is not detectable resets the error flag (input toggling) with the exception of short circuit from out1 to out2 (load short circuit). flag in1 in2 out1 out2 ef remarks nr. open circuit between out1 and out2 0 0 1 1 0 1 0 1 h l l z l h l z 1 1 1 0 not detectable not detectable not detectable 1 2 3 4 short circuit from out1 to out2 0 0 1 1 0 1 0 1 v s /2 v s /2 l z v s /2 v s /2 l z 0 0 1 1 not detectable not detectable 5 6 7 8 short circuit from out1 to gnd 0 0 1 1 0 1 0 1 gnd gnd gnd gnd l h l l 0 1 1 1 not detectable not detectable not detectable 9 10 11 12 short circuit from out2 to gnd 0 0 1 1 0 1 0 1 h l l l gnd gnd gnd gnd 1 0 1 1 not detectable not detectable not detectable 13 14 15 16 short circuit from out1 to v s 0 0 1 1 0 1 0 1 v s v s v s v s l h h h 1 0 0 1 not detectable not detectable 17 18 19 20 short circuit from out2 to v s 0 0 1 1 0 1 0 1 h l h h v s v s v s v s 0 1 0 1 not detectable not detectable 21 22 23 24 overtemperature or undervoltage 0 0 1 1 0 1 0 1 z z z z z z z z 0 0 0 0 25 26 27 28 in: 0 = logic low 1 = logic high out: z = output in tristate condition = v s /2 due to internal pull-up/down resistors ef: 1 = no error 0 = error l = output in sink condition h = output in source condition
tle 5205-2 electrical characteristics data sheet 9 1999-10-07 3 electrical characteristics note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.1 absolute maximum ratings C 40 c < t j < 150 c parameter symbol limit values unit remarks min. max. voltages supply voltage v s C 0.3 40 v C C 1 40 v t < 0.5 s; i s > C 5 a logic input voltage v in1, 2 C 0.3 7 v 0 v < v s < 40 v diagnostics output voltage v ef C 0.3 7 v C currents of dmos-transistors and freewheeling diodes output current (cont.) i out1, 2 C 5 5 a C output current (peak) i out1, 2 C 6 6 a t p < 100 ms; t =1s output current (peak) i out1, 2 C C a t p < 50 m s; t =1s; internally limitted; see overcurrent temperatures junction temperature t j C 40 150 cC storage temperature t stg C 50 150 cC thermal resistances junction case r thjc C 3 k/w p-to220-7-11/12, p-to263-7-1 junction ambient r thja C 65 k/w p-to220-7-11/12 C 75 k/w p-to263-7-1 junction case r thjc C 5 k/w p-dso-20-10 junction ambient r thja C 50 k/w p-dso-20-10
tle 5205-2 electrical characteristics data sheet 10 1999-10-07 3.2 operating range parameter symbol limit values unit remarks min. max. supply voltage v s v uv on 40 v after v s rising above v uv on supply voltage increasing C 0.3 v uv on v outputs in tristate condition supply voltage decreasing C 0.3 v uv off v logic input voltage v in1, 2 C 0.3 7 v C junction temperature t j C 40 150 cC 3.3 electrical characteristics 6 v < v s < 18 v; in1 = in2 = high i out1, 2 = 0 a (no load); C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max. current consumption quiescent current i s CC10main1 = in2 = low; v s = 13.2 v under voltage lockout uv-switch-on voltage v uv on C5.36v v s increasing uv-switch-off voltage v uv off 3.5 4.7 5.6 v v s decreasing uv-on/off-hysteresis v uv hy 0.2 0.6 C v v uv on C v uv off
tle 5205-2 electrical characteristics data sheet 11 1999-10-07 outputs out1, 2 static drain-source-on resistance source i out = C 3 a r ds on h C 220 350 m w 6v < v s < 18 v t j = 25 c C 600 m w 6v < v s < 18 v 350 500 m w v son < v s 6v t j = 25 c C 800 m w v son < v s 6v sink i out = 3 a r ds on l C 230 350 m w 6v < v s < 18 v t j = 25 c C 600 m w 6v < v s < 18 v 400 600 m w v son < v s 6v t j = 25 c C 1000 m w v son < v s 6v note: values of r ds on for v s on < v s 6 v are guaranteed by design. overcurrent source shutdown trippoint C i sdh CC10a t j = C 40 c C8Ca t j = 25 c 6CCa t j = 150 c sink shutdown trippoint i sdl CC10a t j = C 40 c C8Ca t j = 25 c 6CCa t j = 150 c shutdown delay time t dsd 25 50 80 m sC 3.3 electrical characteristics (contd) 6 v < v s < 18 v; in1 = in2 = high i out1, 2 = 0 a (no load); C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5205-2 electrical characteristics data sheet 12 1999-10-07 short circuit current limitation source current C i sch CC20a t < t dsd sink current i scl CC15a t < t dsd open circuit pull up resistor r up 51020k w C pull down resistor r down 51020k w C switching threshold h v eh 22.53vC switching threshold l v eh 22.43vC detection delay time t dsd 25 50 80 m sC output delay times (device active for t > 1 ms) source on t donh C1020 m s i out = C 3 a resistive load sink on t donl C1020 m s i out = 3 a resistive load source off t doffh C25 m s i out = C 3 a resistive load sink off t doffl C25 m s i out = 3 a resistive load 3.3 electrical characteristics (contd) 6 v < v s < 18 v; in1 = in2 = high i out1, 2 = 0 a (no load); C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5205-2 electrical characteristics data sheet 13 1999-10-07 output switching times (device active for t > 1 ms) source on t on h C1530 m s i out = C 3 a resistive load sink on t on l C510 m s i out = 3 a resistive load source off t off h C25 m s i out = C 3 a resistive load sink off t off l C25 m s i out = 3 a resistive load clamp diodes forward voltage high-side v fh C11.5v i f = 3 a low-side v fl C1.11.5v i f = 3 a leakage current source i lkh C 100 C 50 C m aout1 = v s sink i lkl C 50 100 m a out2 = gnd logic control inputs in 1, 2 h-input voltage threshold v inh 2.8 2.5 C v C l-input voltage v inl C1.71.2vC hysteresis of input voltage v inhy 0.4 0.8 1.2 v C h-input current i inh C2 0 2 m a v in = 5 v l-input current i inl C10 C4 0 m a v in = 0 v 3.3 electrical characteristics (contd) 6 v < v s < 18 v; in1 = in2 = high i out1, 2 = 0 a (no load); C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5205-2 electrical characteristics data sheet 14 1999-10-07 error flag output ef low output voltage v efl C 0.25 0.5 v i ef = 3 ma leakage current i efl CC10 m a v ef = 7 v thermal shutdown thermal shutdown junction temperature t jsd 150 175 200 cC thermal switch-on junction temperature t jso 120 C 170 cC temperature hysteresis d t C30CkC shutdown delay time t dsd 25 50 80 m sC note: values of thermal shutdown are guaranteed by design. 3.3 electrical characteristics (contd) 6 v < v s < 18 v; in1 = in2 = high i out1, 2 = 0 a (no load); C 40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 5205-2 electrical characteristics data sheet 15 1999-10-07 figure 4 test circuit overcurrent short circuit open circuit i out i sd i sc i oc ef in1 in2 out1 out2 tle 5205-2 2 3 5 7 1 6 4 4700 f m v s gnd aes02396 i ef in1 i in2 i fl i v ef v in1 in2 v v out1 out2 v r load out1 i out2 i 470 nf fu i ; s i v s 63 v
tle 5205-2 electrical characteristics data sheet 16 1999-10-07 figure 5 switching time definitions figure 6 application circuit aet01994 t t i out = in v source 0 0 3 t donh 50% t rf t 100 ns t doffh i out sink t 50% 20% 80% t onh t offl onl t offh t doffl tt donl 5 a v a 3 0 80% 20% 50% 50% 20% 80% 80% 20% 50% _ < ef in1 in2 m out1 out2 tle 5205-2 2 3 5 7 1 6 4 100 nf + 5 v p m 100 f m v s + v s gnd 2 k w i n = 3 a i bl = 6 a aes02397
tle 5205-2 electrical characteristics data sheet 17 1999-10-07 figure 7 timing diagram for output shorted to ground figure 8 timing diagram for output shorted to v s aed01997 in1, 2 i out1, 2 v ef r short x v fl out1, 2 sch i i sch dsd t i sdh aed01998 in1, 2 i out1, 2 v ef r short x v fu out1, 2 scl i i scl dsd t sdl i s v
tle 5205-2 electrical characteristics data sheet 18 1999-10-07 diagrams quiescent current i s (active) versus junction temperature t j input switching thresholds v inh, l versus junction temperature t j static drain-source on-resistance versus junction temperature t j clamp diode forward voltage v f versus junction temperature t j -50 1 0 150 50 s aed02398 100 c 2 3 4 5 6 7 = 18 v s v j t i ma v = 6 v s 0 aed02400 0.5 1.0 1.5 2.0 2.5 3.0 v inh inl v inh, l v 50 0 -50 c 100 150 t j 0 aed02399 0.1 0.2 0.3 0.4 0.5 0.6 j t low side transistor high side transistor r on 50 0 -50 c 100 150 0.7 aed02401 0.8 0.9 1.0 1.1 1.2 1.3 high side transistor low side transistor v f 50 0 -50 c 100 150 t j
tle 5205-2 electrical characteristics data sheet 19 1999-10-07 overcurrent shutdown threshold i sd versus junction temperature t j error-flag saturation output voltage v ef versus junction temperature t j switching threshold v eh , v eh versus junction temperature t j 0 sd aed02402 2 4 6 8 10 12 i low side transistor high side transistor 50 0 -50 c 100 150 t j -50 0 0 150 50 aed02403 100 c 0.1 0.2 0.3 0.4 0.5 0.6 j t v ef -50 1.8 0 150 50 aed02404 100 c 2.0 2.2 2.4 2.6 2.8 3.0 j t v eh v el v eh , v el
tle 5205-2 package outlines data sheet 20 1999-10-07 4 package outlines p-to220-7-11 (plastic transistor single outline package) typical 0.1 1.27 4.4 9.25 0.2 0.05 1) all metal surfaces tin plated, except area of cut. 2.4 0.5 0.1 0.3 8.6 10.2 0.3 0.4 3.9 0.4 8.4 3.7 0.3 a a 0.25 m 9.8 0.15 2.8 1) 15.65 0.3 13.4 0...0.15 1.27 0.6 0.1 c 0.2 17 0.3 8.5 1) 9.9 0.2 7x -0.15 3.7 10 0.2 6x c 1.6 0.3 gpt09083 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
tle 5205-2 package outlines data sheet 21 1999-10-07 +0.07 -0.02 -0.3 1.2 2.8 1.3 0.25 1) does not include plastic or metal protrusion of 0.15 max. per side 20x 0.25 m 1) heatsink 0.95 14.2 +0.15 index marking 15.9 10 1 0.1 +0.13 0.4 1.27 3.5 max. 0 6.3 11 3.25 20 11 0.15 0.1 0.15 1 x 45? 0.3 5? 3? 0.15 15.74 0.1 a a 1) b 0.25 m b gps05791 p-dso-20-10 (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
tle 5205-2 package outlines data sheet 22 1999-10-07 a 8? max. b a 0.25 m 0.1 typical 9.8 0.15 0.2 10 8.5 1) 8 1) (15) 0.2 9.25 0.3 1 0...0.15 7x0.6 0.1 0.1 1.27 4.4 b 0.5 0.1 0.3 2.7 4.7 0.5 0.05 1) 0.1 all metal surfaces tin plated, except area of cut. 2.4 6x1.27 p-to263-7-1 option e3180 (plastic transistor single outline package) gpt09114 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
tle 5205-2 package outlines data sheet 23 1999-10-07 gpt09084 a b a 0.25 m typical 9.8 0.15 2.8 1) 15.65 0.3 13.4 0...0.15 1.27 0.6 0.1 0.1 1.27 4.4 b 9.25 0.2 0.05 1) all metal surfaces tin plated, except area of cut. c 0.2 17 0.3 8.5 1) 10 0.2 3.7 -0.15 c 2.4 0.5 0.1 13 0.5 0.5 11 7x p-to220-7-12 (plastic transistor single outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm

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